VHDL std_ logic_ Vector index and “downto”

I want to set STD separately_ logic_ Vector to easily annotate individual bits or groups of bits This is what I have:

signal DataOut : std_logic_vector(7 downto 0);
...
DataOut <= (                        5=>'1',-- Instruction defined
                                    4=>'1',-- Data length control bit,high=8bit bus mode selected
                                    3=>'1',-- Display Line Number ctrl bit,high & N3 option pin to VDD=3 lines display
                                    2=>'0',-- Double height font type control byte,not selected
                                    1 downto 0=>"01",-- Select Instruction table1
                                    others=>'0' -- for bits 6,7
                                    );

However, I have questions about the "down to" statement. When using Xilinx ise, the following error occurs:

Type std_ulogic does not match with a string litteral

Avoid using any equivalent solution

1=>'0',0=>'1',

And allow me to set it block by block?

Solution

Assignment x down to y = > when a is an element of an array, 'a' is correct For example, this code snippet is correct:

1 downto 0 => '1',

And this clip is wrong:

1 downto 0 => "01",

Therefore, your task is illegal As your code, you can specify:

DataOut <= (                        5 downto 3 =>'1',2 downto 1 =>'0',0 => '1',others=>'0' 
                                    );

If you want to access / allocate through an array, you can use the connection:

DataOut <= Something_0 & Something_1 & "01";

Although something_* It's STD_ logic_ vector