Multithreading – avoiding cache consistency problems and key parts in Delphi?

I just read an MSDN article "synchronization and multiprocessor issues", which solves the memory cache consistency problem on multiprocessor machines This is really open to me because I don't think there may be a competitive condition in the examples they provide This article explains that writing to memory may not actually occur (from the perspective of other CPUs) in the order in which my code is written This is a new concept for me!

This article provides two solutions:

>Use the volatile keyword for variables that require consistency across multiple CPUs caches This is a C / C + + keyword, which is not available in Delphi. > Use interlockexchange() and interlockcompareexchange() This is what I can do in Delphi if I have to It seems a little messy

The article also mentioned that "the following synchronization functions use appropriate obstacles to ensure memory sorting: • functions that enter or leave key parts"

This is what I don't understand Does this mean that any writes to memory that use the functions of critical parts are not affected by cache consistency and memory sorting problems? I have no objection to the interlock * () function, but another tool in my tool belt will be good!

Solution

First, according to language standards, volatile does not do what the article says Volatile acquisition and release semantics are specific to MSVC This can be a problem if you compile with other compilers or other platforms C 11 introduces language supported atomic variables, hoping to terminate (volatile) at an appropriate time and use volatile as thread construction

The key parts and mutexes have indeed been implemented so that the read and write of protected variables can be correctly seen from all threads

I think the best way to think of key parts and mutexes (locks) is to bring serialized devices That is, the code blocks protected by this lock are executed serially, one after another without overlapping Serialization also applies to memory access There may be no problem due to cache consistency or read / write reordering

The interlocking function is realized by using the hardware based lock on the memory bus These functions are used by lock - free algorithms This means that instead of using heavy locks, such as key parts, they use these lightweight hardware locks

Locking free algorithm can be more effective than lock based algorithm, but locking free algorithm may be difficult to write correctly Like key parts over locking unless the performance impact is discernible

Another article worth reading is the "double checked locking is broken" declaration