VHDL – why can’t I add this ` STD_ logic_ vector`

What happened here? Why do I get an 'operator parameter type mismatch', and what should I do to solve it?

--
-- 32-bit counter with enable and async reset
--
architecture synthesis1 of counter_32bit is    
signal nextvalue : std_logic_vector ( 31 downto 0 );    
begin

  --
  -- combo
  --
  nextvalue <= value + 1; -- here

  --
  -- sequential
  --
  ff:process( clk,rst )
  begin

    if( rst = '1' ) then
      value <= 0; -- and here...
    elsif( clk'event and ( clk ='1' ) ) then
      if( ena = '1' ) then
         value <= nextvalue;
      end if;
    end if;

  end process ff;    

end synthesis1;

thank you

Solution

You cannot increment STD directly_ Logic, you need to use numeric_ The STD package converts it to unsigned and returns the result to STD_ logic_ vector.

use ieee.numeric_std.all
...
nextvalue <= std_logic_vector( unsigned(value) + 1 );

See, for example, how do perform STD_ LOGIC_ VECTOR Addition Using IEEE. NUMERIC_ STD.